All Papers
Author: R. Quislant

2022

Speculative Barriers with Transactional Memory [doi]
M. Pedrero, R. Quislant, E. Gutierrez, E.L. Zapata, O. Plata
IEEE Transactions on Computers, 71 (1), January 2022, pp. 197-208

2021

2020

NATSA: A Near-Data Processing Accelerator for Time Series Analysis [doi][arXiv]
I. Fernandez, R. Quislant, C. Giannoula, M. Alser, J. Gomez-Luna, E. Gutierrez, O. Plata, O. Mutlu
38th IEEE International Conference on Computer Design (ICCD'20), Hardtford (CT, USA), October 2020
(arXiv:2010.02079 [cs.AR])

Energy-Efficient Time Series Analysis Using Transprecision Computing [doi]
I. Fernandez, R. Quislant, E. Gutierrez, O. Plata
IEEE 32nd International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD'20), Porto (Portugal), September 2020

2019

Improving Hardware Transactional Memory Parallelization of Computational Geometry Algorithms Using Privatizing Transactions [doi]
R. Quislant, E. Gutierrez, E.L. Zapata, O. Plata
Journal of Parallel and Distributed Computing, 131, September 2019, pp. 103-119

Barreras Especulativas con Memoria Transaccional [link]
M. Pedrero, R. Quislant, E. Gutierrez, E.L. Zapata, O. Plata
XIX Jornadas de Paralelismo (JJPP'19) (parte de las Jornadas Sarteco), Caceres (Spain), September 2019

2018

Privatizing Transactions for Lee's Algorithm in Commercial Hardware Transactional Memory [doi]
R. Quislant, E. Gutierrez, E.L. Zapata, O. Plata
The Journal of Supercomputing, 74 (4), April 2018, pp. 1676-1694

2017

Mejora de la Escalabilidad de Sistemas de Memoria Transaccional Hardware [link]
R. Quislant, E. Gutierrez, E.L. Zapata, O. Plata
XXVIII Jornadas de Paralelismo (JJPP'17) (parte de las Jornadas Sarteco), Malaga (Spain), September 2017

Lazy Irrevocability for Best-Effort Transactional Memory Systems [doi]
R. Quislant, E. Gutierrez, E.L. Zapata, O. Plata
IEEE Transactions on Parallel and Distributed Systems, 28 (7), July 2017, pp. 1919-1932

Enhancing Scalability in Best-Effort Hardware Transactional Memory [doi]
R. Quislant, E. Gutierrez, E.L. Zapata, O. Plata
Journal of Parallel and Distributed Computing, 104, June 2017, pp. 73-87

Leveraging Irrevocability to Deal with Signature Saturation in Hardware Transactional Memory [doi]
R. Quislant, E. Gutierrez, E.L. Zapata, O. Plata
The Journal of Supercomputing, 73 (6), June 2017, pp. 2525-2557

2016

Irrevocabilidad Relajada para Memoria Transaccional Hardware [link]
R. Quislant, E. Gutierrez, E.L. Zapata, O. Plata
XXVII Jornadas de Paralelismo (JJPP'16) (parte de las Jornadas Sarteco), Salamanca (Spain), September 2016

Insights into the Fallback Path of Best-Effort Hardware Transactional Memory Systems [doi]
R. Quislant, E. Gutierrez, E.L. Zapata, O. Plata
22nd International Conference on Parallel and Distributed Computing (Euro-Par'16), Grenoble (France), August 2016
(Springer, LNCS 9833, P-F. Dutot and D. Trystram, Eds., pp. 251-263)

Exploring Fallback Solutions in Best-Effort Hardware Transactional Memory [link]
R. Quislant, E. Gutierrez, O. Plata
19th Workshop on Compilers for Parallel Computing (CPC’16), Valladolid (Spain), July 2016

2015

Book Chapter: Conflict Detection in Hardware Transactional Memory [doi]
R. Quislant, E. Gutierrez, E.L. Zapata, O. Plata
Transactional Memory: Foundations, Algorithms, Tools and Applications (COST Action Euro-TM IC1001)
(Springer, LNCS 8913, R. Guerraoui and P. Romano, Eds., pp. 127-149, 2015)

Reduccion de la Saturacion en Signaturas Mediante Irrevocabilidad en Sistemas HTM [link]
R. Quislant, E. Gutierrez, E.L. Zapata, O. Plata
XXVI Jornadas de Paralelismo (JJPP'15) (parte de las Jornadas Sarteco), Cordoba (Spain), September 2015

Irrevocable Transactions to Handle Signature Saturation [link]
R. Quislant, E. Gutierrez, O. Plata
18th Workshop on Compilers for Parallel Computing (CPC'15), London (UK), January 2015

2014

Improving Signature Behavior by Irrevocability in Transactional Memory Systems [doi]
R. Quislant, E. Gutierrez, E.L. Zapata, O. Plata
26th International Symposium on Computer Architecture and High-Performance Computing (SBAC-PAD'14), Paris (France), October 2014

Scalability Analysis of Signatures in Transactional Memory Systems [doi]
R. Quislant, E. Gutierrez, O. Plata
26th International Symposium on Computer Architecture and High-Performance Computing (SBAC-PAD'14), Paris (France), October 2014

Dealing with Saturation in Signature-based Transactional Memory Systems [link]
R. Quislant, E. Gutierrez, S. Gonzalez-Navarro, O. Plata
Euro-TM Workshop on Transactional Memory (WTM’2014) (co-located with EuroSys'14), Amsterdam (The Netherlands), April 2014

2013

Exploring Irregular Reduction Support in Transactional Memory [doi]
M.A. Gonzalez-Mesa, R. Quislant, E. Gutierrez, O. Plata
13th International Conference on Algorithms and Architectures for Parallel Processing (ICA3PP'13), Vietri Sul Mare (Italy), December 2013
(Springer, LNCS 8285, Part I, J. Kolodziej, B.D. Martino, D. Talia and K. Xiong, Eds., pp. 257-266)

Dealing with Reduction Operations Using Transactional Memory [doi]
M.A. Gonzalez-Mesa, R. Quislant, E. Gutierrez, O. Plata
25th International Symposium on Computer Architecture and High-Performance Computing (SBACPAD'13), Porto de Galinhas (Brazil), October 2013

Hardware Signature Designs to Deal with Asymmetry in Transactional Data Sets [doi]
R. Quislant, E. Gutierrez, O. Plata, E.L. Zapata
IEEE Transactions On Parallel and Distributed Systems, 24 (3), March 2013, pp. 506-519

LS-Sig: Locality-Sensitive Signatures for Transactional Memory [doi]
R. Quislant, E. Gutierrez, O. Plata, E.L. Zapata
IEEE Transactions On Computers, 62 (2), February 2013, pp. 322-335

2012

Automatic Loop Parallelization Using Transactional Memory Support [link]
M.A. Gonzalez-Mesa, R. Quislant, E. Gutierrez, O. Plata
16th Workshop on Compilers for Parallel Computing (CPC'12), Padova (Italy), January 2012

2011

Unified Locality-Sensitive Signatures for Transactional Memory
R. Quislant, E. Gutierrez, O. Plata, E.L. Zapata
XXII Jornadas de Paralelismo (JJPP’11), La Laguna, Tenerife (Spain), September 2011

Unified Locality-Sensitive Signatures for Transactional Memory [doi]
R. Quislant, E. Gutierrez, O. Plata, E.L. Zapata
17th International Euro-Par Conference on Parallel Processing (Euro-Par’11), Bordeaux (France), August-September 2011
(Springer, LNCS 6852, E. Jeannot, R. Namyst and J. Roman, Eds., pp. 326-337)

Multiset Signatures for Transactional Memory [doi]
R. Quislant, E. Gutierrez, O. Plata, E.L. Zapata
25th International Conference on Supercomputing (ICS'11), Tucson (AZ), USA, May-June 2011

2010

Interval Filter: A Locality-aware Alternative to Bloom Filters for Hardware Membership Queries [link]
R. Quislant, E. Gutierrez, O. Plata, E.L. Zapata
XXI Jornadas de Paralelismo (JJPP'10) (parte de CEDI 2010), Valencia (Spain), September 2010

Interval Filter: A Locality-Aware Alternative to Bloom Filters for Hardware Membership Queries by Interval Classification [doi]
R. Quislant, E. Gutierrez, O. Plata, E.L. Zapata
11th International Conference on Intelligent Data Engineering and Automated Learning (IDEAL'10), Paisley, Scotland (UK), September 2010
(Springer, LNCS 6283, C. Fyfe, P. Tino, D. Charles, C. Garcia-Osorio and H. Yin, Eds., pp. 162-169)

2009

Diseño de Signaturas Explotando Localidad en Memoria Transaccional
R. Quislant, E. Gutierrez, O. Plata, E.L. Zapata
XXI Jornadas de Paralelismo (JJPP'09), A Coruña (Spain), September 2009

Improving Signatures by Locality Exploitation for Transactional Memory [doi]
R. Quislant, E. Gutierrez, O. Plata, E.L. Zapata
18th International Conference on Parallel Architectures and Compilation Techniques (PACT'09), Raleigh (NC), USA, September 2009

Signatures and Locality in Transactional Memory [link]
R. Quislant, E. Gutierrez, O. Plata, E.L. Zapata
5th International Summer School on Advanced Computer Architecture and Compilation for Embedded Systems (HiPEAC ACACES 2009), Terrassa, Spain, July 2009 (poster)

2008

Teaching the Cache Memory System Using a Reconfigurable Approach [doi]
R. Quislant, E. Herruzo, O. Plata, I. Benavides, E.L. Zapata
IEEE Transactions on Education, 51 (3), August 2008, pp. 336-341

2007

Designing a Highly Reconfigurable Cache Memory Architecture
R. Quislant, O. Plata, E. Herruzo, J.I. Benavides
XVIII Jornadas de Paralelismo (JJPP'07), Zaragoza (Spain), September 2007

Simulating a Reconfigurable Cache System for Teching Purposes [doi]
E. Herruzo, J.I. Benavides, R. Quislant, E.L. Zapata, O. Plata
IEEE International Conference on Microelectronic Systems Education (MSE'07), San Diego (CA), USA, June 2007

2006

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