All Papers
Author: E. Herruzo

2022

2021

2020

2019

2018

2017

2016

2015

2014

Top Single Nucleotide Polymorphisms Affecting Carbohydrate Metabolism in Metabolic Syndrome: From the LIPGENE Study [doi]
J. Delgado-Lista, P. Perez-Martinez, J. Solivera, A. Garcia-Rios, A. Perez-Caballero, J.A. Lovegrove, C.A. Drevon, C. Defoort, E.E. Blaark, A. Dembinska-Kiec, U. Riserus, E. Herruzo, J.M. Ordovas, H. Roche, J. Lopez-Miranda
Journal of Clinical Endocrinology & Metabolism, 99 (2), February 2014, pp. E384-E389

2013

2012

Optimizing the PHysical Implementation of a Reconfigurable Cache [doi]
A.D. Santana-Gil, M. Hernandez-Calvino, F.J. Quiles, E. Herruzo, J.I. Benavides
International Conference on Reconfigurable Computing and FPGAs (ReConFig'12), Cancun (Mexico), December 2012

Simulador de Cache Reconfigurable con Unidad de Anticipacion (SICAREAN) [link]
J.A. Perez-Mata, E. Herruzo, J.I. Benavides, O. Plata
XXIII Jornadas de Paralelismo (JJPP'12) (parte de las Jornadas Sarteco), Elche (Spain), September 2012

Experiment with Personal Response Devices - Advantages and Drawbacks Identified in Engineering Studies [link]
F.R. Lara, E. Herruzo, F.J. Jimenez, F.M. Perez, C. Corredor
4th International Conference on Computer Supported Education (CSEDU’12), Porto (Portugal), April 2012

2011

2010

Entrepreneur Features as a Competence in the Design of the European Higher Education Area Degrees [link]
E. Herruzo, R. Espejo, R. Moreno, C. Gonzalez, J.I. Benavides, O. Plata
International Journal of Social, Behavioral, Educational, Economic, Business and Industrial Engineering, 4 (6), June 2010

2009

2008

A Message Passing Implementation of a New Parallel Arrangement Algorithm [doi]
E. Herruzo, J.J. Cruz, J.I. Benavides, O. Plata
International Journal of Electrical and Computer Engineering, 2 (9), September 2008, pp. 3218-3223
(World Academy of Science, Engineering and Technology)

Teaching the Cache Memory System Using a Reconfigurable Approach [doi]
R. Quislant, E. Herruzo, O. Plata, I. Benavides, E.L. Zapata
IEEE Transactions on Education, 51 (3), August 2008, pp. 336-341

Using Padding to Optimize Locality in Scientific Applications [doi]
E. Herruzo, O. Plata, E.L. Zapata
International Conference on Computational Science (ICCS'08), Krakow (Poland), June 2008
(Springer, LNCS 5101, M. Bubak, G.D. van Albada, J. Dongarra and P.M.A. Sloot, Eds., pp. 863-872)

2007

Designing a Highly Reconfigurable Cache Memory Architecture
R. Quislant, O. Plata, E. Herruzo, J.I. Benavides
XVIII Jornadas de Paralelismo (JJPP'07), Zaragoza (Spain), September 2007

Maximum and Sorted Cache Occupation using Array Padding [doi]
E. Herruzo, E.L. Zapata, O. Plata
International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS'07), Samos, Greece, July 2007

Simulating a Reconfigurable Cache System for Teching Purposes [doi]
E. Herruzo, J.I. Benavides, R. Quislant, E.L. Zapata, O. Plata
IEEE International Conference on Microelectronic Systems Education (MSE'07), San Diego (CA), USA, June 2007

A New Parallel Sorting Algorithm Based on Odd-Even Mergesort [doi]
E. Herruzo, G. Ruiz, J.I. Benavides, O. Plata
15th EUROMICRO International Conference on Parallel, Distributed and Network-Based Processing (PDP’07), Naples, Italy, February 2007

2006

Desarrollo e Implementacion de un Algoritmo de Ordenacion Paralelo en OpenMP
G. Ruiz, E. Herruzo, J.I. Benavides, O. Plata
XVII Jornadas de Paralelismo (JJPP'06), Albacete (Spain), September 2006

Optimizing Cache Locality by Static Array Redimensioning [link]
E. Herruzo, E.L. Zapata, O. Plata
12th Workshop on Compilers for Parallel Computing (CPC'06), A Coruña (Spain), January 2006

2005

Medición de los Contadores Hardware del Procesador en Modo Exclusivo
E. Herruzo, P. Navajas, J.I. Benavides
XVI Jornadas de Paralelismo (JJPP'05), Granada (Spain), September 2005

Simulador de Referencias a Memoria en Sistemas Cache Multinivel a Través de Internet
M.A. Herrera, J.M. Palomares, E. Herruzo, J.I. Benavides
XVI Jornadas de Paralelismo (JJPP'05), Granada (Spain), September 2005

Reducing Cache Misses by Loop Reordering [link]
E. Herruzo, G. Bandera, E.L. Zapata, O. Plata
International Conference on Parallel Computing (ParCo2005), Malaga (Spain), September 2005
(Parallel Computing: Current and Future Issues of High End Computing, John von Neumann Institute for Computing, Jülich, Germany, NIC Series Vol. 33, pp. 541-548, 2006)

Distributed Architecture System for Computer Performance Testing [doi]
E. Herruzo, A.J. Mesones, J.I. Benavides, O. Plata, E.L. Zapata
6th International Conference on Parallel Processing and Applied Mathematics (PPAM’05), Poznan (Poland), September 2005
(Springer, LNCS 3911, R. Wyrzykowski, J. Dongarra, N. Meyer and J. Wasniewski, Eds., pp. 140-147)

2004

Distributed Architecture System for Computer Performance Testing using PAPI
J.I. Benavides, J.M. Palomares, A.J. Mesones, E. Herruzo, O. Plata
XV Jornadas de Paralelismo (JJPP'04), Almeria (Spain), September 2004

Applying Loop Tiling and Unrolling to a Sparse Kernel Code [doi]
E. Herruzo, G. Bandera, O. Plata
4th International Conference on Computational Science (ICCS'04), Krakow (Poland), June 2004
(Springer, LNCS 3036, M. Bubak, G. Dick van Albada, P.M.A. Sloot and J. Dongarra, Eds., pp. 409-412)

2003

A Precise Cache Content Analysis to Enable Better Compiler Optimizations
E. Herruzo, G. Bandera, O. Plata
XIV Jornadas de Paralelismo (JJPP'03), Leganes, Madrid (Spain), September 2003

2002

Simulador de Computadora, Servidor de Prácticas Docentes y Sala Temática en Internet
E. Herruzo, J.I. Benavides, G. Bandera
XIII Jornadas de Paralelismo (JJPP'02), Lleida (Spain), September 2002

Aplicacián para la Simulacián del Comportamiento de una Memoria Cache Multinivel
J.I. Benavides, E. Herruzo, G. Bandera
XIII Jornadas de Paralelismo (JJPP'02), Lleida (Spain), September 2002

2001

On Loop Optimizations to Improve the Performance of Sparse Codes
E. Herruzo, G. Bandera, O. Plata
XII Jornadas de Paralelismo (JJPP'01), Valencia (Spain), September 2001

2000

1999

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1997

1996

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