All papers: Last 5 Years
Author: J. Hormigo
2023
HUB Meets Posit: Arithmetic Units Implementation [doi]
R. Murillo, J. Hormigo, A.A. del Barrio, G. Botella
IEEE Transactions on Circuits and Systems II: Express Briefs,
August 2023
2022
High-Radix Formats for Enhancing Floating-Point FPGA Implementations [doi]
J. Villalba, J. Hormigo
Circuits, Systems, and Signal Processing,
41, March 2022, pp. 1683-1703
2021
Introduce MetodologĂas Activas en tu Clase, Indispensable en Tiempos de Pandemia [link]
E. Hendrix, F.M. Castro, D.A. Constantinescu, F. Corbera, S. Gonzalez-Navarro, M. Gonzalez, J. Hormigo, J.R. Cozar, A. Rodriguez
XXXI Jornadas de Paralelismo (JP'20/21) (parte de las Jornadas Sarteco),
Malaga (Spain), September 2021
FPGA Acceleration of Bit-True Simulations for Word-Length Optimization [doi]
J. Hormigo, G. Caffarena
IEEE 28th Symposium on Computer Arithmetic (ARITH'21),
Lyngby, Denmark, June 2021
Efficient Floating-Point Givens Rotation Unit [doi]
J. Hormigo, S.D. Muñoz
Circuits, Systems, and Signal Processing,
40 (5), May 2021, pp. 2419-2442
2020
New Results on Non-normalized Floating-Point Formats [doi]
S. Gonzalez-Navarro, J. Hormigo
IEEE Transactions on Computers,
69 (12), December 2020, pp. 1733-1744
Floating-Point Fused Multiply-Add under HUB Format [doi]
J. Hormigo, J. Villalba, S. Gonzalez-Navarro
IEEE 27th Symposium on Computer Arithmetic (ARITH'20),
Portland (OR, USA), June 2020
2019
Fast HUB Floating-Point Adder for FPGA [doi]
J. Villalba, J. Hormigo, S. Gonzalez-Navarro
IEEE Transactions on Circuits and Systems II: Express Briefs,
66 (6), June 2019, pp. 1028-1032
Reproducible Summation Under HUB Format [doi]
J. Villalba, J. Hormigo, F. Jaime
IEEE 26th Symposium on Computer Arithmetic (ARITH'19),
Kyoto (Japan), June 2019
Designing a Project for Learning Industry 4.0 by Applying IoT to Urban Garden [doi]
J. Hormigo, A. Rodriguez
IEEE Revista Iberoamericana de Tecnologias del Aprendizaje,
14 (2), May 2019, pp. 58-65
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