Final Conference Program

Madrid, Spain. February 14-18, 2004

Saturday, February 14, 2004
All-day Workshops (8:00am - 6:00pm)
SAN-3: Third Annual Workshop on System Area Networks
PPHEC-1: First Workshop on Productivity and Performance in High-End Computing
Half-day Workshops
WEPA-1: First Workshop on Embedded Parallel Architectures (morning)
NP-3: Third Workshop on Network Processors (afternoon)
T-1: Advanced Processor Architectures and Verification Challenges, Sunil Kakkar (8:30am - 12:00pm)
T-2: Power-Aware Design for High-Performance Processors, José González and Kevin Skadron (1:30pm - 5:00pm)

Sunday, February 15, 2004
All-day Workshops (8:00am - 6:30pm)
NP-3: Third Workshop on Network Processors
CAECW-7: Seventh Workshop on Computer Architecture Evaluation using Commercial Workloads
INTERACT-8: Eighth Annual Workshop on Interaction between Compilers and Computer Architecture
Tutorial (8:30am - 12:00pm)
T-3: High-Performance Embedded Computing, Wayne Wolf

Monday, February 16, 2004
Welcome (8:15am - 8:30am)
Keynote I (8:30am - 9:30am)
Chair: José Duato
Microarchitecture: Are we finally done?
    Yale Patt
Break (9:30am - 10:00am)
Session 1: Power Management (10:00am - 12:00n)
Chair: Antonio Gonzalez
Exploiting Prediction to Reduce Power on Buses
    Victor Wen, Mark Whitney, Yatish Patel and John Kubiatowicz
The Thrifty Barrier: Energy-Aware Synchronization in Shared-Memory Multiprocessors
    Jian Li, José F. Martínez and Michael C. Huang
Program Counter Based Techniques for Dynamic Power Management
    Chris Gniady, Y. Charlie Hu and Yung-hsiang Lu
Wavelet Analysis for Microprocessor Design: Experiences with Wavelet-Based dI/dt Characterization
    Russ Joseph, Zhigang Hu and Margaret Martonosi
Lunch (12:00n - 1:30pm)
Session 2: Processor Design I (1:30pm - 3:00pm)
Chair: Oscar Plata
Out-Of-Order Commit Processors
    Adrian Cristal, Daniel Ortega, Josep Llosa and Mateo Valero
Stream Register Files with Indexed Access
    Nuwan Jayasena, Mattan Erez and William Dally
Low-Complexity Distributed Issue Queue
    Jaume Abella and Antonio González
Break (3:00pm - 3:30pm)
Session 3: Prefetching (3:30pm - 5:00pm)
Chair: Anand Sivasubramaniam
Hardware Support for Prescient Instruction Prefetch
    Tor M. Aamodt, Paul Chow, Per Hammarlund, Hong Wang, and John P. Shen
Data Cache Prefetching Using a Global History Buffer
    Kyle Nesbit and James Smith
Processor Aware Anticipatory Prefetching in Loops
    Partha Tirumalai, Spiros Kalogeropulos, Yonghong Song, Mahadevan Rajagopalan and Vikram Rao
Break (5:00pm - 5:15pm)
Panel Session (5:15pm - 7:00pm)
Panel Moderator: Mazin Yousif
Bridging the Research Gap between Academia and Industry
        Mark Hill
        Yale Patt
        Justin Rattner
        Steve Scott
        Antonio Gonzalez
Reception & Cocktail at the Madrid City Hall (7:30pm)
Madrid Guided Tour (8:30pm)

Tuesday, February 17, 2004
Keynote II (8:00am - 9:00am)
Chair: Emilio L. Zapata
Designing for the High End
    Steve Scott
Break (9:00am - 9:15am)
Session 4: I/O (9:15am - 11:15am)
Chair: Timothy M. Pinkston
Reducing Energy Consumption of Disk Storage Using Power-Aware Cache Management
    Qingbo Zhu, Francis David, Yuanyuan Zhou, Cristo Devaraj and Pei Cao
Improving Disk Throughput in Data-Intensive Servers
    Enrique Carrera and Ricardo Bianchini
Synthesizing Representative I/O Workloads for TPC-H
    Jianyong Zhang, Anand Sivasubramaniam, Hubertus Franke, Natarajan Gautam, Yanyong Zhang and Shailabh Nagar
Architectural Characterization of TCP/IP Packet Processing on the Pentium(r) M microprocessor
    Srihari Makineni and Ravi Iyer
TCCA Business Meeting (11:15am - 1:30pm)
Lunch (12:00n - 1:30pm)
Session 5: Caches & Memory I (1:30pm - 3:00pm)
Chair: Josep Torrellas
Signature Buffer: Bridging Performance Gap between Registers and Caches
    Lu Peng, Jih-Kwon Peir and Konrad Lai
Organizing the Last Line of Defense before Hitting the Memory Wall for CMPs
    Chun Liu, Anand Sivasubramaniam and Mahmut Kandemir
Exploiting the Cache Capacity of a Single-chip Multi-core Processor with Execution Migration
    Pierre Michaud
Excursion (3:30pm - 6:30pm)
Banquet (9:15pm)

Wednesday, February 18, 2004
Keynote III (8:30am - 9:30am)
Chair: Yale Patt
Kilo-instructions in-flight Processors
    Mateo Valero
Break (9:30am - 10:00am)
Session 6: Scheduling (10:00am - 12:00n)
Chair: Emilio Luque
Understanding Scheduling Replay Schemes
    Ilhyun Kim and Mikko Lipasti
Creating Converged Trace Schedules Using String Matching
    Satish Narayanasamy, Yuanfang Hu, Suleyman Sair and Brad Calder
Reducing the Scheduling Critical Cycle using Wakeup Prediction
    Todd Ehrhart and Sanjay Patel
Exploring Wakeup-Free Instruction Scheduling
    Jie S. Hu, N. Vijaykrishnan and Mary Jane Irwin
Lunch (12:00n - 1:30pm)
Keynote IV (1:30pm - 2:30pm)
Chair: Francisco Tirado
POWER5 Architecture and Systems
    Balaram Sinharoy
Session 7: Processor Design II (2:30pm - 4:00pm)
Chair: Jose Gonzalez
A Low-Complexity, High-Performance Fetch Unit for Simultaneous Multithreading Processors
    Ayose Falcón, Alex Ramirez and Mateo Valero
Reducing Branch Misprediction Penalty via Selective Recovery
    Amit Gandhi, Haitham Akkary and Srikanth Srinivasan
Using Perceptron-Based Branch Confidence Estimation for Speculation Control
    Haitham Akkary and Srikanth Srinivasan
Break (4:00pm - 4:30 pm)
Session 8: Caches & Memory II (4:30pm - 6:00pm)
Chair: Manuel Prieto
Accurate and Complexity-Effective Spatial Pattern Prediction
    Chi Chen, Se-Hyun Yang, Babak Falsafi and Andreas Moshovos
Using Prime Numbers for Cache Indexing to Eliminate Conflict Misses
    Mazen Kharbutli, Keith Irwin, Yan Solihin and Jaejin Lee
Link-Time Path-Sensitive Memory Redundancy Elimination
    Manel Fernández and Roger Espasa