In conjuction with
Caches have been playing an essential role in the performance of single-core systems due to the gap between processor speed and main memory latency. First level caches are strongly restricted by their access time but current processors are able to hide most of their latency using out-of order execution as well as miss overlapping techniques. On the other hand, last levels of the cache memory hierarchy are not so dependable on their access time but on their locality issues. The locality in lower levels is filtered by the upper levels. As requests going down in the memory hierarchy they require a greater number of cycles to be satisfied, so it becomes more difficult to hide the latency of last-level caches (LLC). In multi-core systems their importance is even large due to the growing number of cores that share the bandwidth that this memory can provide. In an attempt to make a more efficient usage of their caches, the memory hierarchies of many Chip Multiprocessors (CMPs) present LLCs which can be allocated across threads and part of them may be private to a thread while other parts may be shared by multiple threads. Then, caching techniques will continue their evolution during next years in order to tackle the new challenges imposed by multicore platforms and workloads.
The aim of this workshop is to strongly encourage the exchange of experiences and knowledge in novel solutions exploiting and defining new trends in multicore cache hierarchy design, also considering new programming techniques for taking full advantage of cache hierarchies in terms of performance.
The Workshop will be held as a half-day meeting at the ISPA 2012 conference in Leganes, Madrid.
All accepted workshop papers will be published in the ISPA 2012 proceedings.
Authors of accepted papers will be invited to submit an extended version of their manuscript to be considered for publication in a special issue of Concurrency and Computation: Practice and Experience.
The Workshop topics include (but not limited to) the following:
The Workshop is organized by:
Dept. Electronics and Systems, University of A Coruna, Spain
Dept. Computer Architecture, University of Malaga, Spain