ParCo 2005

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A number of Mini-Symposia on special topics related to parallel computing have been organized to be presented together with the regular ParCo2005 program.

This section contains complete information on accepted Mini-Symposia.
Please follow the conference program link to see the schedule of Mini-Symposia contributions.


Mini-Symposium 1
Title: Algorithmic Skeletons and High-Level Concepts for Parallel Programming
Acronym in ParCo program: Algorithmic Skeletons
Organizer: Herbert Kuchen, Westfälische Wilhelms-Univ., Germany
• Integrating MPI-Skeletons with Web Services, J. Dünnweber, A. Benoit, M. Cole, S. Gorlatch, Univ. of Münster, Germany, The Univ. of Edinburgh, Scotland (UK)
• Scalable Farms, M. Poldner, H. Kuchen, Univ. of Münster, Germany
• "Second-generation" Skeleton Systems, M. Danelutto, Univ. of Pisa, Italy
• Domain Decomposition and Skeleton Programming with OCamlP3l, F. Clément, V. Martin, A. Vodicka, R. Di Cosmo, P. Weis, INRIA, France
• Mondriaan Sparse Matrix Partitioning for Attacking Cryptosystems - A Case Study, R.H. Bisseling, I. Flesch, Utrecht Univ., The Netherlands
• Efficient Representation and Parallel Computation of String-Substring Longest Common Subsequences, A. Tiskin, The Univ. of Warwick, UK
• Skeletons for Recursively Unfolding Process Topologies, J. Berthold, R, Loogen, Univ. Marburg, Germany
• Towards Improving Skeletons in Eden, M. Hidalgo-Herrero, Y. Ortega-Mallén, F. Rubio, Univ. Complutense of Madrid, Spain
• Reasoning About Skeletons in Eden, R. Peña, C.M. Segura, Univ. Complutense of Madrid, Spain
• Merging Compositions of Array Skeletons in SAC, C. Grelck, S-B. Scholz, Univ. of Lübeck, Germany, Univ. of Hertfordshire, UK

Mini-Symposium 2
Title: Bioinformatics
Acronym in ParCo program: Bioinformatics
Organizers: José M. Carazo, CNB (CSIC), Spain, Alberto Pascual, Univ. Complutense of Madrid, Spain
• Data Challange on Drug Discovery, V. Breton, CNRS, France
• EMBRACE: a Web Services Grid, A. Bleasby, S. Center, Genome Campus, Hinxton, UK
• Grid Computing as a Key for 3D Reconstruction Parameters Optimization, J.R. Bilbao-Castro, J.M. Carazo, I. García, J.J. Fernández, Univ. of Almería, Spain, CNB (CSIC), Spain
• Services Integration and Task-scheduling in Bioinformatics Grids, S. Ramírez; E. de Andrés, I. Navas-Delgado, A.J. Pérez, J. Aldana, O. Trelles, Univ. of Málaga, Spain
• Submitting Jobs to the EGEE Grid via Web Services in a Workflow Environment, E. de Andrés, N. Jiménez, S. Scheres, J.M. Carazo, Parque Científico de Madrid, Spain, CNB (CSIC), Spain
• Filtering 3D images in Structural Biology with Anisotropic Nonlinear Diffusion on SMP Clusters S. Tabik, E.M. Garzón, I. García, J.J. Fernández, Univ. of Almería, Spain

Mini-Symposium 3
Title: Real-Time / Embedded Systems
Acronym in ParCo program: Real-Time
Organizers: Albert Cheng, Univ. of Houston, USA, Klaus Ecker, TU Clausthal, Germany, Jerome Delatour, ESEO, France
Contributions: Cancelled.

Mini-Symposium 4
Title: Efficient Network-on-Chip Implementation/Emulation Techniques for System-on-Chip Design Exploration
Acronym in ParCo program: NoC
Organizers: Luca Benini, Univ. of Bologna, Italy, Giovanni De Micheli, EPFL, Switzerland, Román Hermida, José M. Mendias, Univ. Complutense of Madrid, Spain
• Networks on Chips: A Synthesis Perspective, F. Angiolini, P. Meloni, L. Benini, S. Carta, L. Raffo, Univ. of Bologna, Italy, Univ. Cagliari, Italy
• Exploration and Tuning of Custom NoC Topologies Using an FPGA-Based Framework, N. Genko, D. Atienza G. De Micheli, EPFL, Switzerland, Univ. Complutense of Madrid, Spain
• Distributed Congestion Control for Packet Switched Networks on Chip, T. Marescaux, A. Rangevall, V. Nollet, A. Bartic, H. Corporaal, IMEC, Belgium, Univ. of Lund, Sweden, Univ. of Eindhoven, The Netherlands
• Versatile FPGA-Based Functional Validation Framework for Networks-on-Chip Interconnections Designs, J.B. Pérez-Ramas, D. Atienza, M. Peón, I. Magán, J.M. Mendias, R. Hermida, INDRA, Spain, Univ. Complutense of Madrid, Spain
• A New Model for NoC-based Distributed Heterogeneous System Design, F. Rincón, F. Moya, J. Barba, D. Villa, F.J. Villanueva, J.C. López, Univ. of Castilla-La Mancha, Spain
• Modular SoC-Design Using the MANGO Clockless NoC, T. Bjerregaard, J. Sparsĝ, S. Mahadevan, J. Madsen, Technical Univ. of Denmark, Denmark

Mini-Symposium 5
Title: Large-Scale Parameter Estimation Problems in Computational Science and Engineering
Acronym in ParCo program: Parameter Estimation
Organizers: Christian Bischof, Martin Bücker, RWTH Aachen University, Germany
Contributions: Cancelled.

Mini-Symposium 6
Title: Tools Support for Parallel Programming
Acronym in ParCo program: Tools Support
Organizer: Bernd Mohr, ZAM (Research Centre Jülich), Germany
• Parallel Performance Mapping, Diagnosis, and Data Mining, A.D. Malony, S. Shende, L. Li, K. Huck, Univ. of Oregon, USA
• Scalability of Tracing and Visualization Tools, J. Labarta, J. Giménez, E. Martínez, P. González, H. Servat, G. Llort, X. Aguilar, CEPBA - UPC, Spain
• Performance Comparison and Optimization: Case Studies using BenchIT, R. Schöne, G. Juckeland, W.E. Nagel, S. Pflüger, R. Wloch, TU Dresden, Germany
• Tools for Petascale and Multi-Paradigm System Design and Evaluation, P.C. Roth, J.S. Vetter, S.R. Alam, N. Bhatia, E.M. Grobelny, M.C. Smith, O.O. Storaasli, Oak Ridge National Lab., USA
• Performance Analysis of One-sided Communication Mechanisms, B. Mohr, A. Kühnal, M.-A. Hermanns, F. Wolf, ZAM (Research Centre Jülich), Germany
• Automated Correctness Analysis of MPI Programs with Intel(r) Message Checker, V. Samofalov, B. Kuhn, J. DeSouza, S. Zheltov, K. Nevidin, V. Krukov, Intel, Russia
• The MPI/SX Collectives Verification Library, J. Worringen, J.L. Träff, NEC C&C Research Lab. St. Augustin, Germany
• MPI Application Development with MARMOT, B. Krammer, M. Müller, Univ. of Stuttgart, Germany

Mini-Symposium 7
Title: Processor Architectures, Instruction Sets and Operating Environments: Where are we going?
Acronym in ParCo program: Processor Architectures
Organizers: Frank Baetke, HP, USA, J. González, Intel Labs, Barcelona, Spain
• AMD Processor Strategy for High Performance Computing, A. Ruiz, AMD, Spain
• Intel's Xeon- and Itanium-based High Performance Processor Strategy, J. González, Intel Labs, Barcelona, Spain
• The POWER Processor Architecture - Details, Status and Trends, M. Hennecke, IBM, Germany
• BlueGene PPC and Cell Architectures: New Paradigms for HPC?, M. Hennecke, IBM, Germany
• The SPARC Processor Architechture - Details, Status and Trends, J.R. Alegret, SUN, Spain
last update: 8 September 2005