All papers: Last 5 Years
Author: J. Villalba

2025

FPHUB-RISCV: HUB Floating-Point Unit in RISC-V Platform - Format definition [link]
J. Hormigo, J. Villalba, G. Bandera, S. Gonzalez-Navarro, A. Martinez-Conejo, A. Fuster, J. Lastre, O. Plata, E.L. Zapata
RISC-V Summit Europe, Paris (France), May 2025

2024

Floating Point HUB Adder for RISC-V Sargantana Processor [arXiv]
G. Bandera, J. Salamero, M. Moreto, J. Villalba
arXiv:2401.09464v1 [cs.AR], January 2024

2023

2022

High-Radix Formats for Enhancing Floating-Point FPGA Implementations [doi]
J. Villalba, J. Hormigo
Circuits, Systems, and Signal Processing, 41, March 2022, pp. 1683-1703

2021