Journal Papers
Author: J. Hormigo

2023

HUB Meets Posit: Arithmetic Units Implementation [doi]
R. Murillo, J. Hormigo, A.A. del Barrio, G. Botella
IEEE Transactions on Circuits and Systems II: Express Briefs, August 2023

2022

High-Radix Formats for Enhancing Floating-Point FPGA Implementations [doi]
J. Villalba, J. Hormigo
Circuits, Systems, and Signal Processing, 41, March 2022, pp. 1683-1703

2021

Efficient Floating-Point Givens Rotation Unit [doi]
J. Hormigo, S.D. Muñoz
Circuits, Systems, and Signal Processing, 40 (5), May 2021, pp. 2419-2442

2020

New Results on Non-normalized Floating-Point Formats [doi]
S. Gonzalez-Navarro, J. Hormigo
IEEE Transactions on Computers, 69 (12), December 2020, pp. 1733-1744

2019

Fast HUB Floating-Point Adder for FPGA [doi]
J. Villalba, J. Hormigo, S. Gonzalez-Navarro
IEEE Transactions on Circuits and Systems II: Express Briefs, 66 (6), June 2019, pp. 1028-1032

Designing a Project for Learning Industry 4.0 by Applying IoT to Urban Garden [doi]
J. Hormigo, A. Rodriguez
IEEE Revista Iberoamericana de Tecnologias del Aprendizaje, 14 (2), May 2019, pp. 58-65

2018

Unbiased Rounding for HUB Floating-Point Addition [doi]
J. Villalba, J. Hormigo, S. Gonzalez-Navarro
IEEE Transactions on Computers, 67 (9), September 2018, pp. 1359-1365

2017

Introduction to the Special Issue on Computer Arithmetic [doi]
J. Hormigo, J. Muller, S. Oberman, N. Revol, A. Tisserand, J. Villalba
IEEE Transactions on Computers, 66 (12), December 2017, pp. 1991-1993

HUB Floating Point for Improving FPGA Implementations of DSP Applications [doi]
J. Hormigo, J. Villalba
IEEE Transactions on Circuits and Systems II: Express Briefs, 64 (3), March 2017, pp. 319-323

2016

New Formats for Computing with Real-Numbers under Round-to-Nearest [doi]
J. Hormigo, J. Villalba
IEEE Transactions on Computers, 65 (7), July 2016, pp. 2158-2168

Measuring Improvement When Using HUB Formats to Implement Floating-Point Systems Under Round-to-Nearest [doi]
J. Hormigo, J. Villalba
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 24 (6), June 2016, pp. 2369-2377

2015

High-Throughput FPGA Implementation of QR Decomposition [doi]
S.D. Muñoz, J. Hormigo
IEEE Transactions on Circuits and Systems II: Express Briefs, 62 (9), September 2015, pp. 861-865

2014

2013

Multioperand Redundant Adders on FPGAs [doi]
J. Hormigo, J. Villalba, E.L. Zapata
IEEE Transactions on Computers, 62 (10), October 2013, pp. 2013-2025

Self-Reconfigurable Constant Multiplier for FPGA [doi]
J. Hormigo, G. Caffarena, J.P. Oliver, E. Boemo
ACM Transactions on Reconfigurable Technology and Systems, 6 (3), October 2013, pp. Art. No. 14

2012

A Study of Decimal Left Shifters for Binary Numbers [doi]
S. Gonzalez-Navarro, J. Hormigo, M.J. Schulte
Journal of Information and Computation, 216, July 2012, pp. 47-56

Radix-2 Multioperand and Multiformat Streaming Online Addition [doi]
J. Villalba, T. Lang, J. Hormigo
IEEE Transactions on Computers, 61 (6), June 2012, pp. 790-803

2011

High-Speed Algorithms and Architectures for Range Reduction Computation [doi]
F.J. Jaime, M.A. Sanchez, J. Hormigo, J. Villalba, E.L. Zapata
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 19 (3), March 2011, pp. 512-516

2010

Enhanced Scaling-Free CORDIC [doi]
F.J. Jaime, M.A. Sanchez, J. Hormigo, J. Villalba, E.L. Zapata
IEEE Transactions on Circuits and Systems I, 57 (7), July 2010, pp. 1654-1662

2009

2008

Pipelined Architecture for Additive Range Reduction [doi]
F.J. Jaime, J. Villalba, J. Hormigo, E.L. Zapata
Journal of Signal Processing Systems, 53 (1-2), November 2008, pp. 103-112

2007

2006

SAD Computation based on On-line Arithmetic for Motion Estimation [doi]
J. Olivares, J. Hormigo, J. Villalba, J.I. Benavides, E.L. Zapata
Microprocessors and Microsystems, 30 (5), August 2006, pp. 250-258

2005

2004

Image Segmentation Using the Wigner-Ville Distribution [doi]
J. Hormigo, G. Cristobal
Advances in Imaging and Electron Physics, Vol. 131, Ed. Elsevier, 2004, pp. 65-80

Estimación de Movimiento en MPEG mediante Técnicas de Aritmética On-Line sobre FPGA [link]
J. Olivares, J. Hormigo, J.I. Benavides, J. Villalba, E.L. Zapata
Revista Iberoamericana de Sistemas, Cibernética e Informática, 1 (2), 2004, pp. 36-41

CORDIC Processor for Variable-Precision Interval Arithmetic [doi]
J. Hormigo, J. Villalba, E.L. Zapata
Journal of VLSI Signal Processing Systems for Signal, Image and Video Technology, 37 (1), May 2004, pp. 21-39

2003

2002

2001

2000

1999

Texture Segmentation Through Eigen-Analysis of the Pseudo-Wigner Distribution [doi]
G. Cristobal, J. Hormigo
Pattern Recognition Letters, 20 (3), March 1999, pp. 337-345

1998

High Resolution Spectral Analysis of Images Using the Pseudo-Wigner Distribution [doi]
J. Hormigo, G. Cristobal
IEEE Transactions on Signal Processing, 46 (6), June 1998, pp. 1757-1763

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