Brief Bio
Rafael Asenjo received his B.S. and M.S. degrees in Telecommunications Engineering in 1993 and his Ph.D. degree in 1997, both from the University of Malaga, Spain. He has been an Associate Professor at the Computer Architecture Dept. Univ. Malaga from 2001 to 2017, and a Full Professor since then. He lectures on computer architecture, operating systems, emerging architectures, accelerating analytics and parallel programming. His research interests include programming models, parallel programming, heterogeneous architectures, parallelizing compilers and multiprocessor architecture.
He was a Visiting Scholar in the Center for Supercomputing Research and Development (CSRD) in the University of Illinois at Urbana-Champaing during 6 months in 1996 and 1997. Later, he was a Postdoctoral Visiting Research Associate in the Department of Computer Science in the UIUC for six months in 1998. During these visits, he did research on automatic parallelization and compilation techniques for multiprocessors under the supervision of Professor David Padua. He also visited IBM T.J. Watson for 4 month in 2008, hosted by Dr. Calin Cascaval. He was also hosted by Dr. Bradford L. Chamberlain to collaborate with the Chapel team in Cray Inc. at Seattle, WA, from June 1 till August 28, 2011. Since then, he contributed to releases 1.4, 1.6 and 1.8 of the Chapel compiler.
Previously, he also was a TRACS visitor in the EPCC center at Edinburgh, UK (1994), a research visitor hosted by Prof. Iain Duff at Centre Européen de Recherche et de Formation Avancée en Calcul Scientifique (CERFACS), Toulouse, France (1996), and also visited the Fakultät für Informatik in the Technische Universität München, Munich, Germany (2000), for a collaborative work with Prof. Michael Gerndt.
He visited the Computer Science Dept. at UIUC (August 2013 and 2014), where he collaborated with María Jesús Garzarán on dynamic load balancing, adaptive mapping and efficient execution of pipeline and parallel for patterns on heterogeneous architectures. More recently, he has visited the Dept. of Electronic and Electrical Eng. at University of Bristol (May 2015 and May-July 2016), where he was collaborating with Dr. Jose Nunez-Yanez in scheduling techniques for heterogeneous chips composed of CPUs, FPGA and GPU. He was granted with the Visiting Fellow honorary academic status at this department from June 2015 till August 2016.
He served as General Chair for ACM PPoPP'16. He has served as an Organization Committee member for CCGrid'17, HPCS'14, PPoPP'11, ParCo'05 and HPCA'04, as well as a Programm Commitee member for SBAC-PAD'18, PACT'17, EuroPar'17, RePara'17, SBAC-PAD'17, SC'15, HIP3ES'17,'16,'15, IPDPS'13,'14, SBAC-PAD'12, PMEA'09 and '10.
Resumé:
• Patents
• Grants
• Teaching